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72 lines
2.1 KiB
72 lines
2.1 KiB
* Generic Phase-Lock_Loop |
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* Internal nodes start at 50. |
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* Internal nodes for a/d and d/a are the node number + 100. |
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* |
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* PLL Subcircuit VCO Parameters |
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* Fc = Center frequency |
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* Fr = Frequency range (center +/- Fr) |
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* Rs = Dem and Vout series resistance |
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* |
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*SPICE code of PLL macromodel |
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*Connections: |
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* Signal In |
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* | Compare In |
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* | | VCO Out |
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* | | | VSS |
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* | | | | Demodulated Out |
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* | | | | | VCO In |
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* | | | | | | Phase Compare |
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* | | | | | | | VDD |
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* | | | | | | | | |
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.SUBCKT PLLX 14 3 4 8 10 9 2 16 PARAMS: Fc=10k Fr=5k Rs=100 |
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*Pin order in SimCode: |
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*INPUTS VCC, GND, SigIn, CompIn; |
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*OUTPUTS PhCompI; |
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*ADC and DAC node bridges |
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A1 [102][2] dac_mod |
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A2 [16 8 14 3][116 108 114 103] adc_mod |
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.model dac_mod xdac |
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.model adc_mod xadc |
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*Self biasing input amplifier consists of two equal resistors (one from SigIn to VDD, |
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*The other from SigIn to ground) and a SimCode buffer with vil at 49.05% and voh at 50.05%. |
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RIN1 14 16 1.5E6 |
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RIN2 14 8 1.5E6 |
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AU4A [116 108 114][154] Apllinbuf |
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.MODEL Apllinbuf xsimcode(file="{MODEL_PATH}pllinbuf.scb" func=pllinbuf) |
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AU1 [116 108 154 103][102] Apllpc1 |
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.MODEL Apllpc1 xsimcode(file="{MODEL_PATH}pllpc1.scb" func=pllpc1) |
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* Scale VCOin to be between 0 and 1 for the XSPICE VCO model. |
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* 1E+15 added to denominator to avoid divide by zero. |
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BNLVs2 53 8 V=( V(9,8)/(V(16,8)+1E-15) ) |
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* Resistor to aid convergance. |
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RCONV1 53 8 100E6 |
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AV1 %vd(53,8) 52 ASQRVCO |
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*SQRVCO Voltage controlled square wave oscillator |
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.MODEL ASQRVCO square(cntl_array=[0 1] |
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+ freq_array=[{(Fc - Fr)} {(Fc + Fr)}] out_low=0 |
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+ out_high=1 duty_cycle=0.5 rise_time=1E-9 fall_time=1E-9) |
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BNLVs4 56 8 V=(V(52) * V(16,8)) + V(8) |
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* Series resistor at NLVs output so that there is not infinite drive. |
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RS1 56 4 {Rs} |
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* Resistor to aid convergance. |
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RCONV2 4 8 100E6 |
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* Demod is isolated from VCOin by a source follower. In this implementation |
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* a NLVs is used instead of a source follower. |
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BNLVs5 55 8 V=V(9) |
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* Series resistor at NLVs output so that there is not infinite drive. |
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RS2 55 10 {Rs} |
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* Resistor to aid convergance. |
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RCONV3 10 8 100E6 |
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.ENDS PLLX
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