diff --git a/Connector.SchLib b/Connector.SchLib index 5482bb9..f1cde79 100644 Binary files a/Connector.SchLib and b/Connector.SchLib differ diff --git a/CustomCase.PcbLib b/CustomCase.PcbLib index 1b248d1..ef8880f 100644 Binary files a/CustomCase.PcbLib and b/CustomCase.PcbLib differ diff --git a/CustomCase2.CMP b/CustomCase2.CMP new file mode 100644 index 0000000..f425f63 --- /dev/null +++ b/CustomCase2.CMP @@ -0,0 +1,14 @@ +Component : CON: TE_1981568-1 +PCB Library : CustomCase2.PcbLib +Date : 28.04.2023 +Time : 14:27:25 + + + +Dimension : 8.839 x 7.087 mm + + Layer(s) Pads(s) Tracks(s) Fill(s) Arc(s) Text(s) +-------------------------------------------------------------------- + Top Overlay 0 35 0 9 1 +-------------------------------------------------------------------- + Total 0 35 0 9 1 diff --git a/CustomCase2.PcbLib b/CustomCase2.PcbLib index 74389da..58d0b82 100644 Binary files a/CustomCase2.PcbLib and b/CustomCase2.PcbLib differ diff --git a/CustomCase2.REP b/CustomCase2.REP new file mode 100644 index 0000000..e6265c0 --- /dev/null +++ b/CustomCase2.REP @@ -0,0 +1,51 @@ +PCB Library : CustomCase2.PcbLib +Date : 28.04.2023 +Time : 14:27:45 + + + +Component Count : 40 + +Component Name +----------------------------------------------- + +CON: JST SM +CON: JST SM03B-GHS-TB +CON: JST SM04B-GHS-TB +CON: JST SM06B-GHS-TB +CON: KLS2-EDR-3.50-2 +CON: KLS2-EDR-3.50-4 +CON: KLS2-EDR-3.81-2 +CON: KLS2-EDR-3.81-4 +CON: L-KLS1-207B-1-02-S +CON: L-KLS1-207B-1-03-S +CON: L-KLS1-XL1-2.00-02-S +CON: L-KLS1-XL1-2.00-03-S +CON: LPJG0926HENL +CON: PLS-2 +CON: TE_1981568-1 +DIP-switch 1H +DIP-switch 1V +DIP-switch 2H +DIP-switch 2V +DIP-switch 4H +DIP-switch 4V +FUSE: MF-MSMF160 +IND: HX5004NL +JMP: PLS-2 +JMP: PLS-3 +KT-0.8mm +KT-1.0mm +LED: 5050x4 +MOD: Black Pill +MOD: CMP10A +MOD: PE18-MS1-IPX +MOD: PE18-MS1-PCB +MOD: PE18-MS1PA1-IPX +MOD: PE18-MS1PA1-PCB +MOD: USB HUB +SW: SS-8 +TR: TDK transformer B78476A8065A003 +USB-B +ZQ: HC-49S +ZQ: HC-49U diff --git a/Diode.SchLib b/Diode.SchLib index d1210e5..e4b8c2d 100644 Binary files a/Diode.SchLib and b/Diode.SchLib differ diff --git a/Electromechanics.SchLib b/Electromechanics.SchLib index 0569321..f558375 100644 Binary files a/Electromechanics.SchLib and b/Electromechanics.SchLib differ diff --git a/Inductor.SchLib b/Inductor.SchLib index 4f81feb..7c1fb27 100644 Binary files a/Inductor.SchLib and b/Inductor.SchLib differ diff --git a/Oscilator.SchLib b/Oscilator.SchLib index 5d0c0a1..8758287 100644 Binary files a/Oscilator.SchLib and b/Oscilator.SchLib differ diff --git a/Project Outputs for dk/dk.IntLib b/Project Outputs for dk/dk.IntLib index 1af8635..404748d 100644 Binary files a/Project Outputs for dk/dk.IntLib and b/Project Outputs for dk/dk.IntLib differ diff --git a/dk.LibPkg b/dk.LibPkg index 70151d5..16c894f 100644 --- a/dk.LibPkg +++ b/dk.LibPkg @@ -364,6 +364,96 @@ OutputName2=PCAD Netlist OutputDocumentPath2= OutputVariantName2= OutputDefault2=0 +OutputType3=CadnetixNetlist +OutputName3=Cadnetix Netlist +OutputDocumentPath3= +OutputVariantName3= +OutputDefault3=0 +OutputType4=CalayNetlist +OutputName4=Calay Netlist +OutputDocumentPath4= +OutputVariantName4= +OutputDefault4=0 +OutputType5=EDIF +OutputName5=EDIF for PCB +OutputDocumentPath5= +OutputVariantName5= +OutputDefault5=0 +OutputType6=EESofNetlist +OutputName6=EESof Netlist +OutputDocumentPath6= +OutputVariantName6= +OutputDefault6=0 +OutputType7=IntergraphNetlist +OutputName7=Intergraph Netlist +OutputDocumentPath7= +OutputVariantName7= +OutputDefault7=0 +OutputType8=MentorBoardStationNetlist +OutputName8=Mentor BoardStation Netlist +OutputDocumentPath8= +OutputVariantName8= +OutputDefault8=0 +OutputType9=MultiWire +OutputName9=MultiWire +OutputDocumentPath9= +OutputVariantName9= +OutputDefault9=0 +OutputType10=OrCadPCB2Netlist +OutputName10=Orcad/PCB2 Netlist +OutputDocumentPath10= +OutputVariantName10= +OutputDefault10=0 +OutputType11=Pcad +OutputName11=Pcad for PCB +OutputDocumentPath11= +OutputVariantName11= +OutputDefault11=0 +OutputType12=PCADnltNetlist +OutputName12=PCADnlt Netlist +OutputDocumentPath12= +OutputVariantName12= +OutputDefault12=0 +OutputType13=Protel2Netlist +OutputName13=Protel2 Netlist +OutputDocumentPath13= +OutputVariantName13= +OutputDefault13=0 +OutputType14=ProtelNetlist +OutputName14=Protel +OutputDocumentPath14= +OutputVariantName14= +OutputDefault14=0 +OutputType15=RacalNetlist +OutputName15=Racal Netlist +OutputDocumentPath15= +OutputVariantName15= +OutputDefault15=0 +OutputType16=RINFNetlist +OutputName16=RINF Netlist +OutputDocumentPath16= +OutputVariantName16= +OutputDefault16=0 +OutputType17=SciCardsNetlist +OutputName17=SciCards Netlist +OutputDocumentPath17= +OutputVariantName17= +OutputDefault17=0 +OutputType18=TangoNetlist +OutputName18=Tango Netlist +OutputDocumentPath18= +OutputVariantName18= +OutputDefault18=0 +OutputType19=TelesisNetlist +OutputName19=Telesis Netlist +OutputDocumentPath19= +OutputVariantName19= +OutputDefault19=0 +OutputType20=WireListNetlist +OutputName20=WireList Netlist +OutputDocumentPath20= +OutputVariantName20= +OutputDefault20=0 [OutputGroup2] Name=Simulator Outputs @@ -799,6 +889,16 @@ OutputName9=Specctra Design PCB OutputDocumentPath9= OutputVariantName9= OutputDefault9=0 +OutputType10=MBAExportPARASOLID +OutputName10=Export PARASOLID +OutputDocumentPath10= +OutputVariantName10= +OutputDefault10=0 +OutputType11=MBAExportSTEP +OutputName11=Export STEP +OutputDocumentPath11= +OutputVariantName11= +OutputDefault11=0 [OutputGroup10] Name=PostProcess Outputs diff --git a/ИМС.SchLib b/ИМС.SchLib index 67fbac5..3722f3e 100644 Binary files a/ИМС.SchLib and b/ИМС.SchLib differ