diff --git a/CustomCase.PcbLib b/CustomCase.PcbLib
index c5234bb..43cad5f 100644
Binary files a/CustomCase.PcbLib and b/CustomCase.PcbLib differ
diff --git a/Diode.SchLib b/Diode.SchLib
index 1f353cd..c527a62 100644
Binary files a/Diode.SchLib and b/Diode.SchLib differ
diff --git a/Modules.SchLib b/Modules.SchLib
index ad822f6..25b3cff 100644
Binary files a/Modules.SchLib and b/Modules.SchLib differ
diff --git a/StandardCase.PcbLib b/StandardCase.PcbLib
index 1801ac7..df2c579 100644
Binary files a/StandardCase.PcbLib and b/StandardCase.PcbLib differ
diff --git a/dk.LibPkg b/dk.LibPkg
index 9935269..eeff649 100644
--- a/dk.LibPkg
+++ b/dk.LibPkg
@@ -714,6 +714,26 @@ OutputName9=Specctra Design PCB
 OutputDocumentPath9=
 OutputVariantName9=
 OutputDefault9=0
+OutputType10=Orcad v7 Capture Design
+OutputName10=Orcad v7 Capture Design (AutoSCH)
+OutputDocumentPath10=
+OutputVariantName10=
+OutputDefault10=0
+OutputType11=P-CAD ASCII
+OutputName11=P-CAD ASCII (AutoPCB)
+OutputDocumentPath11=
+OutputVariantName11=
+OutputDefault11=0
+OutputType12=P-CAD V16 Schematic Design
+OutputName12=P-CAD V16 Schematic Design (AutoSCH)
+OutputDocumentPath12=
+OutputVariantName12=
+OutputDefault12=0
+OutputType13=SiSoft
+OutputName13=SiSoft (AutoPCB)
+OutputDocumentPath13=
+OutputVariantName13=
+OutputDefault13=0
 
 [OutputGroup10]
 Name=PostProcess Outputs
diff --git a/ИМС.SchLib b/ИМС.SchLib
index 0c728a9..9e91bba 100644
Binary files a/ИМС.SchLib and b/ИМС.SchLib differ