diff --git a/Connector.SchLib b/Connector.SchLib
index d1887e1..5a313ad 100644
Binary files a/Connector.SchLib and b/Connector.SchLib differ
diff --git a/CustomCase.PcbLib b/CustomCase.PcbLib
index f4353c1..a53580c 100644
Binary files a/CustomCase.PcbLib and b/CustomCase.PcbLib differ
diff --git a/dk.LibPkg b/dk.LibPkg
index 1420fa7..0b9c25d 100644
--- a/dk.LibPkg
+++ b/dk.LibPkg
@@ -156,7 +156,7 @@ ClassGenCCAutoRoomEnabled=1
 ClassGenNCAutoScope=None
 DItemRevisionGUID=
 GenerateClassCluster=0
-DocumentUniqueId=
+DocumentUniqueId=VHHIGNKH
 
 [Document8]
 DocumentPath=ИМС.SchLib
@@ -697,6 +697,26 @@ OutputName9=Specctra Design PCB
 OutputDocumentPath9=
 OutputVariantName9=
 OutputDefault9=0
+OutputType10=Orcad v7 Capture Design
+OutputName10=Orcad v7 Capture Design (AutoSCH)
+OutputDocumentPath10=
+OutputVariantName10=
+OutputDefault10=0
+OutputType11=P-CAD ASCII
+OutputName11=P-CAD ASCII (AutoPCB)
+OutputDocumentPath11=
+OutputVariantName11=
+OutputDefault11=0
+OutputType12=P-CAD V16 Schematic Design
+OutputName12=P-CAD V16 Schematic Design (AutoSCH)
+OutputDocumentPath12=
+OutputVariantName12=
+OutputDefault12=0
+OutputType13=SiSoft
+OutputName13=SiSoft (AutoPCB)
+OutputDocumentPath13=
+OutputVariantName13=
+OutputDefault13=0
 
 [OutputGroup10]
 Name=PostProcess Outputs
diff --git a/ИМС.SchLib b/ИМС.SchLib
index a705205..9a81387 100644
Binary files a/ИМС.SchLib and b/ИМС.SchLib differ